1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit having a function of detecting the occurrence of latch up, and further to a semiconductor integrated circuit having a function of making a recovery from latch up at the occurrence thereof.
2. Description of Related Art
In recent years, as circuit system applications are diversified, there have been more cases of using a configuration in which a circuit block that operates between a positive potential and a ground potential (GND) and a circuit block that operates between a positive potential and a negative potential are formed on a common semiconductor substrate. For this configuration, generally, a semiconductor integrated circuit with a so-called triple well structure is used in which a N-type diffusion (N-well) layer is formed in a P-type substrate (P-sub) layer, and a P-type diffusion (P-well) layer is formed further in the N-type diffusion layer.
Furthermore, in a CMOS integrated circuit, with respect to a P-type diffusion layer and a N-type diffusion layer on a common semiconductor substrate, a n-channel MOS transistor (NMOS) is formed on the P-type diffusion layer, and a p-channel MOS transistor (PMOS) is formed on the N-type diffusion layer.
In the circuit block that operates between a positive potential and a negative potential in the above-described semiconductor integrated circuit with the triple well structure, a ground potential is applied to the P-type substrate layer, a positive potential that usually is a power supply voltage potential is applied to the N-type diffusion layer, and a negative potential that usually is a lowest potential is applied to the P-type diffusion layer. Further, depending on a circuit configuration, in some cases, a negative potential is connected to a source of a n-channel MOS transistor that is formed on the P-type diffusion layer, and a drain thereof is connected to an input terminal or an output terminal of the semiconductor integrated circuit and thus is connected to the exterior of the semiconductor integrated circuit. In such a case, applying the positive potential to the N-type diffusion layer allows the N-type diffusion layer to play a role as a channel stopper, and thus even in the case where a potential of each terminal of the n-channel MOS transistor becomes lower than that of the P-type substrate layer, a parasitic diode is prevented from being turned on, thereby allowing a normal circuit operation to be performed. However, when a potential lower than a back-gate voltage that is a potential supplied to the P-type diffusion layer is applied to the drain of the n-channel MOS transistor, latch up, which refers to a state where an abnormal current flows continuously from the P-type substrate layer connected to the ground potential to the negative potential, might occur.
The following describes a principle by which such latch up occurs with reference to FIGS. 14 and 15.
FIG. 14 is a cross-sectional structural view of a semiconductor integrated circuit with a typical triple well structure including a n-channel MOS transistor. As shown in FIG. 14, in the semiconductor integrated circuit with the triple well structure, a N-type diffusion layer 102 is formed in a P-type substrate layer 101, and a P-type diffusion layer 103 is formed in the N-type diffusion layer 102.
A N-type impurity is implanted into the P-type diffusion layer 103 so that a drain 104 and a source 105 are formed, and a gate 106 is formed on a portion of a substrate between the drain 104 and the source 105 via an unshown insulating film, thereby constituting a n-channel MOS transistor 107. Further, a back gate 108 that is a P-type contact region is formed in the vicinity of the source 105.
Herein, the source 105 of the n-channel MOS transistor and the back gate 108 are connected to a negative potential VSS. Further, the P-type substrate layer 101 is connected to a ground potential via a high-concentration impurity region 110, and the N-type diffusion layer 102 is connected to a power supply voltage potential VDD via a high-concentration impurity region 109. Moreover, the drain 104 of the n-channel MOS transistor 107 is connected to a terminal A that is linked to the exterior of the semiconductor integrated circuit.
In this case, in the semiconductor integrated circuit shown in FIG. 14, a double emitter parasitic npn transistor 111 that uses the drain 104 and the source 105 of the n-channel MOS transistor as a double emitter, the power supply voltage potential VDD to be applied to the N-type diffusion layer 102 as a collector, and the P-type diffusion layer 103 as a base, and a parasitic pnp transistor 112 that uses the P-type substrate layer 101 as an emitter, the P-type diffusion layer 103 as a collector, and the N-type diffusion layer 102 as a base, are formed. Further, a parasitic resistance 113 is formed between the P-type substrate layer 101 and the ground potential (GND), a parasitic resistance 114 is formed between the N-type diffusion layer 102 and the power supply voltage potential VDD to be applied thereto, and a parasitic resistance 115 is formed between the P-type diffusion layer 103 and the back gate 108.
FIG. 15 shows a thyristor structure formed by the parasitic elements of the semiconductor integrated circuit including the n-channel MOS transistor shown in FIG. 14. In FIG. 15, when a voltage lower than VSS is applied to the terminal A of the double emitter parasitic npn transistor 111, a base-emitter (terminal A) voltage increases, so that the parasitic npn transistor 111 is turned on. It is conceived that a base current that flows at this time when the parasitic npn transistor 111 begins to be turned on is supplied from the negative potential VSS.
A collector current of the parasitic npn transistor 111 makes an electric current flow from VDD via the parasitic resistance 114 in the N-type diffusion layer 102 and leads a base current of the parasitic pnp transistor 112 thereinto. When the voltage applied to the terminal A decreases further, the collector current of the parasitic npn transistor 111 increases, and a base potential of the parasitic pnp transistor 112 decreases, so that the parasitic pnp transistor 112 is turned on. An emitter current of the parasitic pnp transistor 112 flows from the ground potential (GND) via the parasitic resistance 113 in the P-type substrate layer 101. Further, a collector current of the parasitic pnp transistor 112 flows to the parasitic resistance 115 in the P-type diffusion layer and to the base of the parasitic npn transistor 111.
In the end, a latch up state is reached in which a base potential of the parasitic npn transistor 111 increases, and even with no voltage applied to the terminal A, an electric current continues to flow to the emitter of the parasitic npn transistor 111, which is connected to the negative potential VSS. Among conditions for which latch up persists at this time is a voltage level of the negative potential. Generally, latch up is liable to persist when VSS has a value not higher than −1 V, though this value may vary depending on the type of a semiconductor process.
As a measure to prevent the occurrence of such latch up, on a semiconductor substrate, layout structural consideration has been given to set the parasitic resistance 114 in the N-type diffusion layer 102 and the parasitic resistance 115 in the P-type diffusion layer 103 to have a low resistance value. However, the above-described measure based on the layout on the semiconductor substrate has an effect that may vary depending on a characteristic of a semiconductor process that is used, and in some cases, it is impossible to sufficiently prevent the occurrence of latch up.
With this as a background, a technique has been proposed that provides a unit that detects the occurrence of latch up and achieves a recovery from the latch up (see Patent Document 1). With reference to FIGS. 16 and 17, the following describes a configuration of a detection unit that detects the occurrence of latch up, which is described in Patent Document 1.
FIG. 16 is a cross-sectional structural view of a CMOS integrated circuit showing a configuration of a unit that detects the occurrence of latch up in Patent Document 1. In the CMOS integrated circuit shown in FIG. 16, a N-type diffusion layer 122 is provided in a P-type substrate layer 121.
A P-type impurity is implanted into the N-type diffusion layer 122 so that a source 123 and a drain 124 are formed, and together with a gate 125 between them, the source 123 and the drain 124 constitute a p-channel MOS transistor 126. Meanwhile, a N-type impurity is implanted into the P-type substrate layer 121 so that a source 127 and a drain 128 are formed, and together with a gate 129 between them, the source 127 and the drain 128 constitute a n-channel MOS transistor 130.
Furthermore, as shown in FIG. 16, the N-type diffusion layer 122 is connected to a power supply voltage potential VDD via a high-concentration impurity region 131, and VDD is connected to the source of the n-channel MOS transistor 126. Further, the P-type substrate layer 121 is connected to a ground potential (GND) via a high-concentration impurity region 133, and the source 127 of the n-channel MOS transistor 130 also is connected to the ground potential. The drain 124 of the p-channel MOS transistor 126 and the drain 128 of the n-channel MOS transistor 130 are connected to each other and then connected to an output terminal Vout of the CMOS integrated circuit.
In the above-described CMOS integrated circuit described in Patent Document 1 and shown in FIG. 16, a N-contact region 132 is formed in a portion of the N-type diffusion layer 122 between the p-channel MOS transistor 126 and the high-concentration impurity region 131, and a P-contact region 134 is formed in a portion of the P-type substrate layer 121 between the n-channel MOS transistor 130 and the high-concentration impurity region 133.
In this case, in the CMOS integrated circuit, a first parasitic pnp transistor 141 that uses the source 123 of the p-channel MOS transistor 126 as an emitter, the N-type diffusion layer 122 as a base, and the P-type substrate layer 121 as a collector, and a second parasitic pnp transistor 142 that uses the drain 124 of the p-channel MOS transistor 126 as an emitter, the N-type diffusion layer 122 as a base, and the P-type substrate layer 121 as a collector, are generated. Further, a first parasitic npn transistor 144 that uses the source 127 of the n-channel MOS transistor 130 as an emitter, the P-type substrate layer 121 as a base, and the N-type diffusion layer 122 as a collector, and a second parasitic npn transistor 143 that uses the drain 128 of the n-channel MOS transistor 130 as an emitter, the P-type substrate layer 121 as a base, and the N-type diffusion layer 122 as a collector, are generated.
Moreover, a resistance component 145 as a diffusion resistance is formed in a portion of the N-type diffusion layer 122 between the high-concentration impurity region 131 and the N-contact region 132, and a parasitic resistance 146 is formed between the N-contact region 132 and the N-type diffusion layer 122. Further, a resistance component 147 as a diffusion resistance is formed in a portion of the P-type substrate layer 121 between the high-concentration impurity region 133 and the P-contact region 134, and a parasitic resistance 148 is formed between the P-contact region 134 and the P-type substrate layer 121.
FIG. 17 shows a thyristor structure of the parasitic elements generated in the CMOS integrated circuit shown in FIG. 16.
In this case, when a potential of the output terminal Vout becomes higher than the power supply voltage potential VDD, a trigger current flows in from the emitter of the second parasitic pnp transistor 142 and flows through the parasitic resistance 148, thus causing a voltage drop. Due to this voltage drop, a base potential of the first parasitic npn transistor 144 increases, so that the first parasitic npn transistor 144 is turned on. When the first parasitic npn transistor 144 is turned on, a collector current of the first parasitic npn transistor 144 flows though the resistance component 145 and the parasitic resistance 146. At this time, a voltage drop is observed in a potential Vnw of a detection terminal of the N-type diffusion layer 122, which is connected to the N-contact region 132, and thus the occurrence of latch up can be detected based on this voltage drop. Similarly, a voltage drop is observed in a potential Vp-sub of a detection terminal of the P-type substrate layer 121, which is connected to the P-contact region 134, thereby allowing the occurrence of latch up to be detected.
In the CMOS integrated circuit described in Patent Document 1, when the occurrence of latch up is detected, the power supply voltage potential VDD is reduced to 0 V to be cut off so that a latch up state is allowed to cease, thereby achieving a recovery from the latch up.    Patent Document 1: JP 9(1997)-116022 A